The present invention generally relates to a heterojunction bipolar transistor (HBT) and a manufacturing method thereof. More particularly, the present invention relates to a self-aligned heterojunction bipolar transistor and a manufacturing method thereof.
Shrinking of transistor dimensions is required for reduced parasitic resistance and reduced parasitic capacitance in heterojunction bipolar transistors (HBTs) and for higher operation speed, higher integration, and lower power consumption. Self-aligned HBTs are advantageous for shrinking of transistor dimensions, and a method for forming an undercut region in a semiconductor layer that forms an emitter has been actively used among the manufacturing processes of self-aligned HBTs. In this manufacturing process, an emitter electrode is formed on a semiconductor layer that forms an emitter, and then, side etching is conducted to the semiconductor layer to form an undercut region that is recessed with respect to the emitter electrode. Thereafter, a metal film for forming an electrode is formed by vapor deposition. The emitter electrode and the base electrode are simultaneously and separately formed from this metal film. In this method, the distance between the emitter region having a mesa structure of fine dimensions and the base electrode can be reduced as much as possible, whereby parasitic base resistance can be reduced significantly.
The most convenient method for conducting side etching to a semiconductor layer that forms an emitter is to conduct selective wet etching by using an emitter electrode as a mask. When wet etching is conducted to a GaAs- or InP-based compound semiconductor, the compound semiconductor commonly has a trapezoidal shape or an inverted-trapezoidal shape (a trapezoid whose upper base is longer than the lower base) depending on its crystal orientation. This shape influences the limit of shrinking of transistor dimensions in view of the contact area between the emitter layer and the layers formed on and under the emitter layer. In order to realize a fine self-aligned InP/InGaAs HBT having an InGaAs base layer, Japanese Laid-Open Patent Publication No. 11-186278 (Japanese Patent No. 3,350,426) discloses an optimal material and optimal heat treatment conditions for a T-shaped stacked emitter electrode in an emitter mesa cross-sectional structure.
The conventional method for manufacturing a self-aligned HBT will be described with reference to FIGS. 4A to 4C. FIGS. 4A to 4C are cross-sectional views illustrating a conventional manufacturing process of a self-aligned HBT.
In the conventional manufacturing method, a collector contact layer 114, a collector layer 115, a base layer 116, an emitter layer 117, and an emitter contact layer 118 are sequentially formed on an InP substrate 113 in this order in the step of FIG. 4A. A WSi layer 119 is then deposited on the entire surface of the emitter contact layer 118 by a sputtering method. A Ti/Pt electrode layer 120 is then formed on the WSi layer 119 by a lift-off method.
In the step of FIG. 4B, by using the Ti/Pt electrode layer 120 as a mask, the exposed part of the WSi layer 119 is selectively removed by an RIE (Reactive Ion Etching) method using sulfur hexafluoride (SF6). Side etching is then conducted to the part of the WSi layer 119 which is covered by the Ti/Pt electrode layer 120. A T-shaped stacked emitter electrode 121 is thus formed from the Ti/Pt electrode 120 and the WSi layer 119 that has a smaller area than that of the Ti/Pt electrode 120.
Thereafter, the following three-step etching is conducted by using the T-shaped stacked emitter electrode 121 as a mask: first, the emitter contact layer 118 is anisotropically etched in the depth direction (the direction perpendicular to the substrate surface) by an ECR-RIE (Electron Cyclotron Resonance-Reactive Ion Etching) method by using a chlorine-argon (Cl2-Ar) mixed gas diluted with an inert gas. Thereafter, side etching is conducted to the emitter contact layer 118 by using a selective wet etchant that is formed from citric acid, hydrogen peroxide solution, and water. As a result, an undercut portion 125 that is recessed with respect to the T-shaped stacked emitter electrode 121 is formed in the emitter contact layer 118. Finally, by using a wet etchant that is formed from hydrochloric acid and phosphoric acid, the InP emitter layer 117 is selectively etched so that the region of the InP emitter layer 117 which is not covered by the emitter contact layer 118 is removed. As a result, the InGaAs base layer 116 is exposed.
In the step of FIG. 4C, a metal layer 122 for forming a base electrode is formed on the top surface of the T-shaped stacked emitter electrode 121 and on the top surface of the InGaAs base layer 116 by electron beam evaporation. The metal layer 122 is a Pt/Ti/Pt/Au layer. In this way, a semiconductor device having a self-aligned emitter/base mesa structure can be manufactured.
As described above, in the conventional manufacturing method, anisotropic dry etching and wet etching are sequentially conducted as etching for forming the undercut portion 125 in the emitter layer in order to improve dimensional control and to prevent emitter-base short-circuiting. However, this wet etching shapes the emitter contact layer 118 into a trapezoidal shape, thereby limiting shrinking of dimensions.